1. Field of the Invention
The present invention relates to a three-dimensional high frequency inductor, its module and fabrication method of the same; the passive components, such as miniaturized high frequency inductors, filters, resistors, capacitors are associated with active components or power components to form an integrated circuit, then it is packaged by using the technology of flip chip or wafer level packaging, so as to upgrade the properties of high frequency modules and reduce the packaging and measurement costs by minimizing the modular size.
2. Description of the Prior Art
Rapid growth in technological development of mobile communication has stimulated need of high frequency radio devices a great deal. The prosperity of radio communication products depends a lot on the size of their component parts and durability of batteries used. Accordingly, the component manufacturers have been doing their efforts in developing components which are more effective yet smaller in size and cheaper in cost than ever. The ultimate goal of minimizing these components is to combine them with an integrated circuit (IC) to form a system-on-chip (SOC). However, there is a big problem in forming SOCs by combining varieties of function provided by different suppliers, since a considerably long time is required for transferring techniques pertaining to particular intellectual property and combining products and fabricating processes which are individually developed by different manufacturers. To cope with the above depicted situation, it is absolutely necessary to establish a systematic technology of combining varieties of wafers, dies provided by different manufacturers and instrumentation processes of dies in advance so as to improve yield rate and to save packaging cost. At the same time, through establishment of perfect customization, intellectual property can be surely protected. In order to minimize product size, power consumption and electro-magnetic interference, to decrease complexity of fabrication process and to improve portability of the products in a relatively low cost way, the combination of active components made of wafers with different fabrication processes and materials with IC circuit modules of high density passive components to form high density IC SOC by packaging process is preferably feasible.
At present, there are two series of high frequency module products composed of combined passive components having competitive force in fabrication technique and product cost. The first one is a thin film high frequency module compatible with IC manufacturing process, the second one is a low temperature co-fired ceramic (LTCC) module with a very high durability for high frequency power as its greatest advantage, but there are a lot of outstanding problems still have to be resolved, for examples, insufficient line width, difficulty in measurement, difficulty in obtaining the ceramic powder, and occurrence of ceramic shrinkage during fabrication process etc. Therefore, severe deviation between fabrication process and simulation result is occurred and which is difficult to rectify. As for fabrication cost, it appears no significant difference between two series of products mentioned above, but the thin film combined high frequency module has a tangible superiority of its smaller product size, and is able to combine active circuit components to realize systematic simulation so as to be benefited by saving, research cost and shortening research time.
A high frequency module requires many passive components in it, and occupies a considerably large space. These passive components are composed of resistors, capacitors, inductors, conductors, coupling wire or transducers. In the passive components, resistors and capacitors which can be easily figured out with simple formula with fewer problems for performance. While the inductor, which being a magnetic element, is relatively tedious procedure. The most commonly used inductor at present is one formed in a planar spiral configuration which can be easily manufactured with advantages of low noise and very small power consumption, but on the contrary, it is disadvantageous because of a bulky size and an unstable inductance value influenced by fabrication process and a low quality factor. Especially, in a planar spiral inductor used in IC, mutual induction between its magnetic line of force with the IC substrate further exacerbates degrading the Q (quality factor) value of device and resulting in a low efficiency of the device.
For achieving the object of improving the property of the inductors in a high frequency module, it is a commonly adopted method to lower the loss of the substrate and minimize the resistance of the metal layer. Means for lowering the substrate loss includes using a high impedance substrate, etching the part of the substrate beneath the inductor, interlarding a thin isolation layer (SGS or PGS), or a porous silicon oxide layer (OPS) between the inductor and the substrate. While the means for minimizing the resistance of the metal layer includes using a thick metal layer, connecting a plurality of metal layers in parallel, or adopting electroplating process etc. Besides, an elaborate circuital layout is another feasible solution.
In the past decade, benefited by rapid growth of the technology for fabricating micro-electromechanical elements, a three-dimensional spiral inductor becomes compatible in an IC so as to replace a conventional planar spiral inductor. As for representative fabrication methods for this new type of inductor are: applying three-dimensional laser molding or surface micro electro-mechanical technology so as to keep the area required for an inductor as small as possible, and at the same time allowing the effect of substrate parasitic capacitance.
FIG. 1a through FIG. 1f are schematic views of structure for a planar spiral inductor and fabrication process of same in U.S. Pat. No. 5,844,299 pertaining to American National Semiconductor Co. The conventional silicon substrate of a suspended inductor is removed by etching, but herein the inductor is suspended on the silicon substrate by means of micro-electro-mechanical technique. As shown in FIGS. 1a and 1b, using photo-lithographic method, a predetermined etching region 12 is defined on a substrate 10 by photo resistance 11, next, etching is carried out by an etchant so as to form a cavity 13; then, as shown in FIGS. 1c and 1d, forming a sacrificial layer 14 on the cavity 13 by coating and polishing the surface thereof smooth (as shown in FIG. 1e); after that, as shown in FIG. 1f, forming a supporting layer 15 and an inductance metallic pattern 1b on the smoothed sacrificial layer 14; finally, removing the sacrificial layer 14 so as to complete a suspended inductor.
FIGS. 2a and 2b are schematic views of structure for a three-dimensional solenoid inductor in U.S. Pat. No. 6,008,102 pertaining to Motorola Co. As shown in these two drawings, a buffer layer 26 and a seed layer 25 are grown on a substrate 20, then the three-dimensional solenoid inductor 21 is constructed by means of a first photo-resistive layer 22, a second photo-resistive layer 23, and a third photo-resistive layer 24 wherein the metal for forming the inductor 21 is essentially made by electroplating, the seed layer 25 is necessary to be included between the metal layers for stacking up the inductor 21. This type of inductor are quite different from a planar spiral inductor in that its inductance varies in proportional to the number of turns. This is a very important and valuable feature in designing a three-dimensional solenoid inductor. On the contrary, the inductance of a planar spiral inductor can not maintain a linear relationship with its number of turns but is influenced by the parasitic and coupling capacitances between the silicon substrate and the metal layer. Accordingly, it is difficult to estimate an accurate value of inductance. Furthermore, the spacing between spiral turn also affect the quality factor of the inductor. If the spacing is too small, the inductance will decrease notwithstanding the quality factor is improved by increasing density of magnetic fluxes there between. There are several advantages concerning the solenoid inductor: a good inductor on the silicone substrate, an inductance in linear relationship with number of turns, the shorten distance between adjacent coils thereby minimizing the size of the inductor, and the provision of thicker metal layer so as to improve ability for withstanding high current. But instead of its high quality, stability of the three dimensional structure is apt to be influenced by bonding force between layers provided by the seed layer 25 for the reason that the inductor is electroplated. Especially, the final fabrication processes, i.e. packaging, and application in mobile communication, the unpreventable shock or vibration will definitely affect its property. Besides, the three-dimension solenoid inductor is able to shorten the distance between coils to decrease its size, but it is difficult to avoid resonance arising from the inductance and the capacitance distributing between the inductor windings. As a result, inductance of the inductor varies as the frequency is changed, and from worse to worst, the inductor's behavior deviates far apart from an inductor and approaches a capacitor. Accordingly, minimizing above mentioned distributing capacitance as low as possible is important for widening applicable frequency range for this high frequency module.